Reflex CES Introduces FPP25 ASIC/SOC Prototyping Platform Print E-mail
Written by Chelsey Drysdale   
Monday, 11 February 2013 17:01

FPP25 ASIC/SOC prototyping platform is for emulating designs of up to 25 million ASIC gates. Is based on Xilinx Virtex-7 2000T FPGAs. Integrates Flexras Wasga automatic partitioning design suite, offering partitioning, timing analysis and pin-multiplexing solutions. Can optionally add Adacsys AVA (advanced verification acceleration) software, as well as Xilinx Vivado Design Suite and Xilinx ChipScope debugging tools. Operates with a GbE interface, a USB interface, or a 4-lane PCIe cable. Each FPGA intercommunicates by nearly 400 LVDS signals at 1.25Gbps. An onboard CPU with an embedded Linux operating system is implemented to handle the configuration and monitoring functions. Up to 5 platforms can be changed together to address high-density designs of more than 125 million ASIC gates.

Reflex CES, http://www.reflexces.com/en/

 

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