First fix the foundation: the stackup, vias and power delivery network.

High-speed PCB design of a differential pair or a bus assumes a sound high-speed board has been designed as the foundation. If mistakes were made or too many shortcuts taken, high-speed signals become the first to die, like the proverbial canary in the mine shaft. Faster, smaller designs make assumptions about high speeds – those design “rules of thumb” – unlikely to stay true. Here we will extend good high-speed design into properly designing the board stackup, vias and power delivery network (PDN). Then, as high-speed traces are routed, you are staged for success instead of redesign.

A fast and small example. The iPhone board is a great example of fast – a 1 GHz processor – and small. This PCB defines small as just big enough to hold the ICs. Less than an inch by two to three inches is normal for small PCBs. If the definitions for via manufacturing and stackups aren’t changed, as soon as a BGA is placed, you have two big problems: power distribution and return currents.

A traditional through-hole via array starves the copper under the BGA (Figure 1), and there is no longer a significant plane area somewhere else. This causes the power distribution network to be vulnerable to two fatal problems: First, current density peaks will result in DC voltage droop, and second, plane inductance becomes significant enough at these frequencies that the high-speed bypass capacitance won’t work right.

Power plane design considerations remain the same with small footprints, but for small boards with high-speed logic, two issues go from good ideas to essential. Plane pairing for higher-frequency supply capacitance must be a starting point for the stackup and the planes must be as whole as possible.

Planning the return path plane and keeping that plane whole is also a necessary ingredient, not just for a quality design, but also for a functional design. This means finding or planning a good plane stackup, putting layer constraints on high-speed routes, and only punching vias through routing layers, not planes. All these design needs point to the same conclusion: high density interconnect (HDI) technology. If HDI is considered to be unfeasible or too expensive, talk to the fabricator. Using the outermost layers as buildup to permit blind and buried vias is less expensive than adding layer pairs to the stackup. Take a closer look at Figure 2, an iPhone board cross-section. A stackup does not have to be invented from scratch. Many of the best variations have already been dreamed up, with documentation on which layers to constrain high-speed channels. For example, start from the PCB West 2012 presentation “The Science of PCB Stackups” by Susy Webb. And while you are at it, take advice from another PCB West presentation, “Decoupling Placement,” by Vern Wnek.

Get it right. Smaller power planes do not afford the luxury of over-designing the PDN. There is space only to use the right amount of bypass, mounted optimally.

While using via-in-pad for other HDI routing benefits, also use it for low inductance mounting of bypass capacitors. This makes them much more effective in the same board real estate. Another thing that dramatically affects board space needed for bypass capacitance is plane capacitance. Notice in the iPhone cross-section that the plane separation is very narrow. With less surface area to work with, the dielectric constant and thickness become important design numbers.

Hopefully it was obvious to support the good design techniques by showing simulation results (Figure 3). This is a perfect example of the best mixture of design artistry and math. It is a complete waste of time to jump straight to simulation and park there for weeks. This will only define for you exactly how bad it was to ignore experience and common sense.

 
Start with the knowledge gained from experience to get to a tight design with fundamentally sound beginnings. Then, before the first trace is routed, start simulating both the PDN and the planned high-speed routes. Simulations early on will reveal any unexpected problem spots. The earlier they are found, the easier they are to fix or even avoid in the first place. A prime example is a small plane with a corner where a current bottleneck is okay, but not great. You have to accommodate the shape of the board, but if you lose any copper on that plane near the corner, it just won’t be in spec anymore and will usually result in lower manufacturing yields. Finding this at the onset is no problem, as routes can be planned around this limitation. Finding it later becomes a redesign to get back to functionality.

High-speed design, whether small boards or large and complex, have the same need for good design practices supported by simulation. There are a handful of critical concerns, especially the PDN and return paths. With these types of boards, HDI fabrication, as well as power integrity and signal integrity simulation, goes from “good idea” to normal and necessary.

Randall Myers is a technical marketing engineer at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .