The maximum number of layers in a flex circuit depends on the design and engineering behind it.

When meeting with a new client or engineer, I am often asked, “What is the maximum number of layers a flex circuit can have?”

Like many “general” questions there’s the quick answer and there’s the right answer. My quick answer is “eight,” but the more correct answer may be “it depends.”

We live by many design “rules,” but any engineer or PCB designer will admit to bending these rules on occasion. The key is to know how and when to bend these rules, and how to use proper FMEA procedures to mitigate risk.

Close attention to basic design rules becomes critical when we build a flex above six layers. At eight layers we need to pay close attention to every aspect of the design. The application has to be reviewed for basic electrical and mechanical requirements and a determination made as to the impact the material stackup will have on both. Are we looking at a “formed” flex, or is our circuit used in a dynamic application? For this exercise we are going to review two real-world eight-layer flex circuits (both type 3), one completed years ago and another of more recent vintage.

Let’s start with a quick review of what concerns us when we design a high layer-count flex: What potential failure modes are we likely to experience?

Obviously as we add layers, we add thickness. Each additional layer in turn requires an additional layer of adhesive. Our enemy here is coefficient of thermal expansion (CTE). In our first example, our design required vias, specifically plated through-holes. Though leaded components requiring PTHs have become less common, there are still a large number of connectors and devices that require them (this is especially true in military applications). The more layers we add, the more stresses we are placing on the PTH, or plated barrel, during thermal excursions or thermal shock. In many cases it may not be as important to count the number of layers but to review the overall thickness of the entire flex.

IPC guidelines call for a minimum of 25µm of copper plating on flex of six layers or fewer, while requiring 35µm on boards greater than six layers. This is regardless of actual board thickness. To be fair, these are indeed guidelines; no specification could possibly account for every possible variation within a circuit type. Regardless of the recommendations, it is important to review the stackup carefully, examine the operating environment of the flex, and determine what we believe to be the best course to take. Remember, these guidelines are minimums; it is up to us to determine if we require more for our particular application.

Figure 1 shows the older eight-layer design. It has every electrical and mechanical requirement the designer could think of: high current requiring heavy copper (multiple layers of 2 oz. copper); impedance control requiring thick dielectrics (differential pairs on layers 2 and 3); shielding to control EMI. And of course, let’s not forget our through-holes. This design came in at a whopping 49 mils thick!

Our second potential failure mode was forming. While this design was clearly not capable of active flexing, it did require multiple complex bends and forming. Extreme care had to be taken in calculating minimum forming radii and bend angles. Care in conductor routing through bend zones was required. In this instance, while the additional adhesive added to our CTE issues, it assisted in forming by permitting a more relaxed bend radius. This took considerable strain off the conductors during the forming process.

Normally in this situation I would have recommended moving to a type 4 construction (rigid-flex), but the number of signals and conductors running through the flex area would not allow it.

Consumer electronics and many commercial applications have packed more functionality in thinner and lighter constructions, a trend that shows no sign of abating. This puts a literal “squeeze” not only on the flex circuit but also the engineer who needs to satisfy this demand. A flex of 49 mils just won’t do. That brings us to our next eight-layer board with an entirely different set of requirements.

This application has to bend and flex repeatedly. Undreamed of even a few years ago, the advent of new materials has permitted these types of constructions. Even with conventional line width and space, we can take advantage of HDI (high density interconnect) via technology and design features to create our thin eight-layer flex. No through-holes here! Blind and buried are the best bet. Stacked or filled vias can take the place of through-holes where no-lead components are required. No long barrels means significantly reduced CTE concerns. Adhesive thickness and copper weights are brought down to the absolute minimums permitted by design. Moving to adhesiveless substrates further reduces the amount of adhesive in the stackup. Our second eight-layer is exactly one-third the thickness of the first.

The only thing these two flex circuits have in common is layer count. Both had entirely different mechanical and electrical requirements that needed to be taken into consideration before their design could be finalized. Both have their place in differing markets.

Our first eight-layer example required a heavy FMEA and several prototype runs. It also required intensive quality testing at each fabrication step. Yes, it was a success, but at significant cost and effort. Our later eight-layer required little in the way of FMEA and could move quickly from prototype to production. Building higher count multilayers requires careful consideration: not all eight-layer boards are equal. I dare say that with today’s rapid development of thinner substrates and lower copper weights, our design rules can quickly become outdated. We must reexamine our rules constantly lest we become victims of them.

Mark Verbrugge is a field applications engineer at PICA Manufacturing Solutions (picasales.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . He and co-“Flexpert” Mark Finstad ( This e-mail address is being protected from spambots. You need JavaScript enabled to view it ) welcome your questions.