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Written by Mike Buetow   
Monday, 02 December 2013 19:48

Component Packaging

“Higher Density PoP Semiconductor Packaging Solution: Bridging the Infrastructure Gap between Wire-Bond and TSV Interconnect”

Authors: Vern Solberg, Charles Woychik, Wael Zohni and Ilyas Mohammed; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: This paper introduces an ultra high-IO package-on-package (PoP) that significantly increases bandwidth, and a package assembly process featuring a very low profile stacked-die memory variation developed for high-performance SDRAM. For the former (called BVA), a high-density PoP test vehicle initially designed for this development program has a 14 x 14mm package outline and more than 400 240µm pitch interconnects between the lower and upper package sections. The interconnect process developed for the BVA uses copper bond-wire that can furnish an array configured contact pitch at or below 200µm. This interconnect solution is economical and lends itself to a wide variety of 3D PoP packaging applications. For the latter (xFD), a very thin dual and quad face-down die stacking solution has been developed for high-performance DDR3 and DDR4 memory. It uses a unique offset die mounting scheme and through-slot wire-bond process to overcome limitations of current vertically configured face-up/face-down wire-bond interface solutions that exhibit a nonuniform or excessively long wire-bond interface. (SMTA International, October 2013)

Reliability

“Solder Joint Reliability”
Authors: Jose M. Servin and Cynthia Gomez; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: The origin of solder cracking can be a real challenge, especially when the failure mode is unknown. For that, the crack topographic study reveals the crack type and consequently what stress could have caused it. This paper shows analyses of four real cases covering several situations. The first unit showed striation marks and concentration of solder phases, with solder grinded down by stress – evidence of potential thermal-stress fatigue. Next, the thermo-vibration fatigue failure had provoked more micro cracks, which derivates a catastrophic crack and the solder joint fracture; intermetallic clusters and changes in the distribution of solder phases were also observed. In the third unit, a hit in high temperature below solder melting point made a more uniform crack surface compared to the first two; the intermetallics from pin-solder can be seen, although some solder plastic deformations are observed. Finally, a mechanical hit provoked a crack along the intermetallic layer. All were investigated to find the root causes, and in some the failure mode was reproduced to check the consistency of the results. (SMTA International, October 2013)

SMT Assembly

“Enhancing Mechanical Shock Performance Using Corner Bond Technology”
Authors: Steven Perng, TaeKyu Lee and Cherif Guirguis; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Corner bond adhesive material has been widely used for improving shock performance of area array packages. Most of the studies focus on impact of material properties, such as CTE and Tg, on reliability at room temperature. However, the operating temperature of a large chassis system with the printed circuit board filled with corner bond material can be close or over Tg of corner bond material. And, the material properties may exhibit different characteristics as the temperature crossing Tg. The objective of this study was to investigate the possible shock performance degradation of corner bond material at elevated temperature. An eight-layer 5" x 5" x 0.093" high-Tg, FR-4 test vehicle was used. A 1mm pitch, 52.5mm FCBGA with 2597 SAC 305 balls was mounted in the center of the test vehicle. Two different pad layouts are included in the DoE, which are full NSMD and NSMD with 35 SMD pads in each of the four corners. Three corner bond materials with different Tg were tested, with no corner bond as the benchmark. The shock test conditions were per JESD22-B110A and performed at two different temperature levels, room temperature and 100°C. The preliminary results indicated the shock performance can be degraded as the temperature increases from room temperature to 100°C. Degradation was more significant for the lower Tg corner bond material. The test results also indicated the corner SMD pad design may have adverse impact on shock performance at elevated temperature, compared to the full NSMD pad design. In summary, when using corner bond material as an enhancement tool for shock performance, users may need to take operating temperature into consideration during material selection. (SMTA International, October 2013)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Last Updated on Monday, 02 December 2013 22:28
 

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