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Written by E. Jan Vardaman   
Monday, 01 July 2013 17:57

ECTC attendees search for winning solutions in Las Vegas.

As the 63rd Electronics Components and Technology Conference (ECTC) drew to a close, the record number of more than 1,300 attendees discussed the latest developments in electronics packaging, materials, and assembly late into the night in a neon-lit strip of Las Vegas. While many presentations discussed drivers for 3D ICs where die are vertically connected with through silicon vias (TSVs), commercialization still seems like a desert mirage, leaving attendees thirsting for alternative packaging solutions.

The plenary session set the stage for much of the conference discussion, providing insight into the future role of wafer foundries in next-generation packaging. Participants from TSMC, GlobalFoundries, UMC, IBM and SMIC captivated a packed room with insights. TSMC discussed its chip-on-wafer-on-substrate (CoWoS) reference design that incorporates the use of a silicon interposer. While TSMC has a pilot line for assembly of early products, it will not “go it alone” for all packaging activities and emphasized work with its assembly partners for high-volume applications. GlobalFoundries discussed challenges in package adoption and drivers, using the example of RF devices moving from quad flat no-lead (QFN) packages to wafer-level chip size packages (WLCSP) driven by footprint and cost.

While system-on-chip (SoC) has been touted by many as the ultimate solution, it can no longer be the answer to lower cost because die are becoming so large that defect densities result in low yields that drive up costs. Examples include leading-edge graphics processors and other products. The focus is on disaggregation and systems-level savings where some IC functions will be kept at optimal nodes and the use of silicon interposers provides a communication path between the chips. The focus is on improving yields in everything to enable cost reduction. UMC described the supply-chain integration between the foundry and the outsourced assembly and test subcontractor (OSAT) in its “Open Eco System.” IBM listed the driver for new packaging solutions as mobile data where the exponential growth in data rates is creating the need for new hardware architecture designs that enable the CPU to access data faster. Scaling of transistors to reduce cost will not be possible with the more expensive lithography tools required for future technology nodes, especially at the 7nm silicon node. IBM calls the trend back to the future in that multichip modules (MCMs) will be the answer, except this time it will be in the form of 3D stacking. The 2.5D or silicon interposer plans can address nearer term needs before 3D ICs with TSVs are ready for prime time. IBM described its use of SiGe in an RF application. IBM also discussed the potential for photonics for high I/O transmission. SMIC echoed many of the earlier points, but emphasized how 2.5D and 3D IC fit into the supply chain. All panel members agreed that cost is a limiting factor, and responding to audience questions, emphasized the need for higher yield, test methodologies, and known good die to achieve 3D IC commercialization. The distinguished panel exuded an aura of cooperation with assembly partners and customers to enable the industry to meet future electronic product needs.

A plethora of packaging options. While commercialization timelines continue to push out for 3D IC structures, many other packaging options received considerable attention. A number of papers discussed use of silicon interposers and potentially glass for a 2.5D solution. Papers from Xilinx and TSMC described production examples, and several papers detailed developments in silicon and glass interposers. A special session provided some excellent presentations on 3D reliability, including interposers and stacked die structures.

Discussions also focused on improvements in wafer-level packaging with both conventional fan-in technology and fan-out technology. Embedded components, especially discrete passives and potentially active devices, received renewed attention. Many presentations discussed developments in flip-chip interconnect for CSPs and large die packages. New material developments to improve performance and reliability were described.

A panel session on LEDs for solid-state lighting provided a glimpse into the latest developments in the packaging of LEDs and the promise for growth in this area. A special session at the conference was devoted to high brightness LEDs and material developments.

Another evening session focused on packaging challenges across the wireless market supply chain with speakers from Nokia, Qualcomm, RFMD, Amkor, and Samsung Electro-Mechanics (SEMCO). This panel discussion addressed monolithic silicon integration versus 3D IC, or what Nokia called “super chips.” Panelists agreed that small spaces in mobile devices create special thermal challenges. Potential problem areas also include materials and processes to handle ultra low-k devices, assembly with fine pitch copper pillar bumps with less than 100µm pitch, handling ultra thin die (<150µm thickness), CTE mismatch, and substrate warpage in thin-core and coreless substrates. Numerous papers throughout the conference addressed many of these issues.

A special session discussed modeling and simulation challenges in 3D systems. Papers throughout the conference provided modeling developments for this area and others, including MEMS, glass and silicon interposers, memory, and logic. The final evening session focused on advanced low-loss dielectric materials for high-frequency and high-bandwidth applications. There are promising materials on the horizon including new build-up dielectrics.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Her column appears bimonthly.

Last Updated on Monday, 01 July 2013 21:36
 

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