Valor IPO Could Bring $80M Print E-mail
User Rating: / 0
PoorBest 
Written by Administrator   
Monday, 14 January 2008 22:43
YAVNE, ISRAEL – Software provider Valor Computerized Systems plans an initial public offering of ordinary shares, according to a Securities and Exchange Commission filing.

The company did not disclose the expected size or price range of the IPO, but indicated the planned March offering may net up to $80.5 million.

The company plans to offer $50 million of shares, while shareholders will make an offer to sell of up to an additional $20 million of their shares and underwriters will be granted options for an additional $10.5 million worth of shares.

For the nine months ended Sept. 30, Valor's earnings were $2.2 million on revenue of $31.4 million.
 
Valor, currently traded on the Frankfurt Exchange, said its new symbol will be "VLOR." 
 
blog comments powered by Disqus
 

Products

ANSYS Releases Ansoft Designer 6.0
Ansoft Designer 6.0 Solver on Demand technology analyzes signal-integrity, power-integrity and electromagnetic interference problems from a single schematic- and layout-based environment. Can access field and circuit simulation tools while designing electronic packages and PCBs early in the design cycle. Integrates HFSS 3-D electromagnetic field simulation software and HSPICE IC simulation. Can predict how high-frequency electromagnetic components affect ICs. Provides user interface to HSPICE with direct links to HFSS and access to the ANSYS QuickEye and VerifEye convolution and statistical...

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 

Features

In Case You Missed It
Component Layout“PCB Design and Assembly for Flip-Chip and Die Size CSP”Author: Vern Solberg; vsolberg123@aol.com.Abstract: This paper outlines the basic elements furnished in the newly released IPC-7094, Design and Assembly Process Implementation for Flip-Chip and Die Size Components, providing a comparison of existing and emerging wafer-level and chip-size package methodologies. The focus is on the effect of PCB design and assembly of bare die or die-size components in an uncased or...

Current Issue

June 2010 cover

Parts


Find and quote components




Powered by


Terms Of Use

Printed Circuit Design & Fab Magazine on Facebook