| Fifth International Wafer-Level Packaging Conference Set for Oct. 13-16 |
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| Written by Philip Buonpastore | |||
| Monday, 07 January 2008 12:08 | |||
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SAN JOSE, CA - This year's International Wafer-Level Packaging Conference and Tabletop Exhibition will expand to four days, from October 13 through 16, at the Wyndham Hotel. This year's conference will include half-day workshops by Dr. Ken Gilleo, inventor, international lecturer, and author of seven books on semiconductors, MEMS and nanotechnology trends and packaging. Dr. Gilleo will reportedly present two workshops on MEMS and nanotechnology covering aspects of 3D/stacked packaging, flip chips, testing advanced devices, wafer-level packaging and emerging technologies, such as the design and fabrication of through-silicon vias. Emerging technologies will reportedly also include a workshop on solar processing and packaging, and a panel discussion on how photovoltaics will impact the semiconductor and related industries. The keynote dinner will be held on October 15. Dr. Thomas H. DiStefano, president of Centipede Systems, whose work at Tessera in San Jose helped propel chip-scale packaging into the mainstream, will be the keynote speaker. The conference will feature more than 50 companies exhibiting and demonstrating their products and services for attendees.
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| Last Updated on Wednesday, 30 January 2008 11:19 |
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Sensor Products Introduces Tactilus Heat-Sink Analysis System
Tactilus heat-sink analysis system enables test and correction of surface contact and pressure distribution between the heat sink and its source. Can visualize actual contact forces and pressure distribution data on the components. As mounting screws between the CPU and the heat sink are torqued, it maps and measures the changing pressure distribution between the mating surfaces and displays it. Can be tested, manipulated, and repositioned in real-time. Provides pressure data needed for FEA simulation predictions. Is 0.015" thick; can be placed between the CPU and heat sink without affecting...
Tactilus heat-sink analysis system enables test and correction of surface contact and pressure distribution between the heat sink and its source. Can visualize actual contact forces and pressure distribution data on the components. As mounting screws between the CPU and the heat sink are torqued, it maps and measures the changing pressure distribution between the mating surfaces and displays it. Can be tested, manipulated, and repositioned in real-time. Provides pressure data needed for FEA simulation predictions. Is 0.015" thick; can be placed between the CPU and heat sink without affecting...
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