Allegro 16.6 printed circuit board CAD accelerates timing closure for high-speed interfaces by 30 to 50% through timing-aware physical implementation and verification, delivered in electrical CAD (ECAD) team collaboration environment for PCB design using Microsoft SharePoint technology. Components can now be embedded vertically on an innerlayer of a PCB leveraging the z-axis, greatly reducing x- and y-axis real estate on the board. Auto-interactive Delay Tuning (AiDT) lessens time to meet timing constraints on advanced standards-based interfaces, such as DDR3, by 30 to 50%. Rapidly adjusts timing of critical high-speed signals on an interface-by-interface basis, or at byte-lane level, reducing need to tune traces on a PCB from days to hours. Is integrated with EMA Timing Designer for achieving timing-closure on critical high-speed signals. PCB/enclosure co-design is streamlined through an ECAD-MCAD flow based on EDMD schema version 2.0, a proStep iViP standard. Reduces iterations between ECAD and MCAD teams, shortening time for product creation.

Cadence Design Systems, www.cadence.com

See Cadence at PCB West 2012 conference and exhibition, Sept. 25-27, Santa Clara, CA booth #206