The Road to Solar Competitiveness Print E-mail
Written by Tom Falcon   
Tuesday, 03 January 2012 20:26



The benchmarks are aggressive, but progress is being made.

What sits at the foundation of widespread solar adoption is no huge secret: The technology has to be inexpensive (relative to fossil fuel power generation), broadly available, reliable long-term and self-sustaining. So, it’s not so much what lies at the end of the road that’s debatable; it’s the milestones along the journey that warrant discussion.

The recently published International Technology Roadmap for Photovoltaics (ITRPV)1 sheds light on the aggressive advances in all areas – material use, manufacturing equipment output and process developments – required to significantly reduce cost and raise efficiency of solar-generated electricity. The study, which centers on crystalline-silicon (c-Si) solar cell/module processes and materials (c-Si cells, incidentally, account for nearly 80% of today’s installed solar modules), points out that while the cost of solar modules has been reduced by about 17% to 25% (according to its historical learning curve), this trend has to continue at an aggressive pace over the next decade in order to achieve the overall cost-reduction goals. Among some of the eye-opening, cost-lowering strategies outlined in the report are silicon price reductions of 50% or more (until 2020), new manufacturing equipment and processes that can cope with much thinner wafers (part of the 50% silicon price reduction scenario), development of Pb-free pastes that deliver equal or better performance to current materials, silver consumption reductions, equipment throughput capacity improvements and new cell designs and technologies. Whew! That’s a lot to take in on this road trip.

Is all this achievable and, equally important, attainable in a respectable time frame? Yes and yes. In fact, the good news is that much of this work is already underway and considerable progress made toward achieving these objectives. Of course, my expertise lies with the cell metallization process and, speaking from a relative position of experience, metallization and printing techniques are, in some cases, ahead of what the ITRPV outlines.

Let’s start with the silicon cost-reduction strategy and the corresponding wafer handling criteria. In addition to the base price of silicon being reduced, most of the silicon overhead savings is to be achieved through the use of thinner (i.e., less silicon) wafers. The ITRPV report cites current average wafer thicknesses at 180µm, moving to 160µm in 2012, and by 2020, the wafer thickness needs to be at 100µm to achieve the proposed 50% silicon cost reduction. For the manufacturing side, that means being able to handle delicate substrates, while ensuring very low breakage rates. Solutions already developed include metallization platforms with zero-edge-contact handling, wafer transport systems that delicately load/unload wafers, and materials deposition strategies that permit robust paste transfer with exceptionally controlled pressure to eliminate breakage concerns.

Silver consumption decreases and finer line printing are also two areas of the cost-competitive strategy outlined by the ITRPV. The report suggests reducing paste consumption in the near term (the next one to three years) to help lessen the impact of high silver costs and, in the longer term, moving to Cu-based materials. In September, I addressed the silver conundrum and outlined how technologies such as print-on-print (PoP) and dual print, along with a change of materials, can significantly lower cost. This is precisely in line with the ITRPV data. Not only does the PoP approach apply to silver reduction, but also addresses the piece of the technology roadmap that calls for finer-line printing and line width. PoP effectively narrows the width and raises the conductor finger height so that less shadowing occurs without a sacrifice to conductivity and efficiency. This technique recently made headlines when the Institute for Solar Energy Research Hamelin (ISFH) reported that PoP technology was a central component to its record-setting 19.4% cell efficiency.2 Currently, the finger width for PoP sits at 60µm. The ITRPV calls for that measurement to be reduced to a mere 30µm, with alignment accuracy better than 10µm for more complex cell structures by 2020. In a lab environment, our company has demonstrated 50µm PoP finger widths, with dual-print widths down to 35µm.

Not surprisingly, cell production is going to require large economies-of-scale to meet cost-reduction targets. Translation: greater equipment throughput for both front- and backend cell processes, plus matching, equal capacity for both process areas. I can’t speak for front-end chemical and thermal equipment companies, but I can certainly comment on metallization throughput. The current roadmap has set a metallization/classification throughput target of 3600 wafers per hour (wph) by 2013, doubling to 7200 wph by 2020, an objective we are well on track to meet.

There also are several other critical components in the drive toward solar cost-competitiveness. These include new higher efficiency, lower cost assembly cell designs, such as back contact (MWT and EWT) and efficiency-enhancing technologies like selective emitter (which, incidentally, requires extremely accurate printing for a good result), among others.

Buckle up! The ride is going to be intense, but rewarding.

References

1. International Technology Roadmap for Photovoltaics Results 2010, Second Edition, March 2011.
2. “DEK Solar Helps Enable Record 19.4% Cell Efficiency at ISFH,” DEK press release, May 2011.

Tom Falcon is a senior process development specialist at DEK Solar (dek.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . His column runs bimonthly.

Last Updated on Tuesday, 03 January 2012 23:53
 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 


Printed Circuit Design & Fab Magazine on Facebook