Cadence Challenges Hardware Development Process Print E-mail
Written by Mike Buetow   
Wednesday, 28 April 2010 19:14

SAN JOSE -- Cadence Design issued a challenge to the semiconductor and electronic design automation communities to address the growing "profitability gap" that threatens the vitality of the electronics industry.

According to the plan, which Cadence calls EDA360 vision, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. “The EDA industry now stands at a crossroads where it must change in order to continue as a successful, independent market. Without this change, EDA will struggle to solve the increasingly complex problems customers are facing now and in the future,” Cadence said in a press release.

Cadence asserts hardware development precedes that of software, a “disaggregated development approach” that confines later OS and application development.
Moreover, game-changing entrants focused on application innovation and differentiation require semiconductor providers to supply "application-ready" platforms with hardware and software for a given application such as mobile computing.

To counter that, a new Cadence white paper ( outlines an application-driven development model where hardware is designed and developed to dynamically meet the needs of the application.

“EDA360 provides an expanded, 360-degree vision of a revitalized EDA industry that serves integrators as well as creators. EDA360 will close the profitability gap through integration-ready IP creation, integration, and optimization,” Cadence said. “With EDA360, we start with an understanding of the software applications that will run on a given hardware/software platform, define system requirements, and then work our way down to hardware/software IP creation and integration.”

In support of an environment that will foster its vision, Cadence is working on technical collaboration (it just announced one with Wind River), and what it calls the first fully integrated, high-performance verification computing platform to unify simulation, acceleration and emulation into a single verification environment.

The announcements targeted semiconductor and system-on-chip development, however, and it is unclear at present what role, if any, PCB design holds within Cadence’s eda360 roadmap.





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