New Webinar Details Chip-Board Debug Print E-mail
Written by Mike Buetow   
Thursday, 12 December 2013 13:58

RICHARDSON, TX – A new tutorial by Asset InterTech investigates how advanced test and debug tools based on instruments embedded in chips are able to identify the root causes of defects and variances in complex chips and circuit boards. “What we’ve seen is that in an era of shrinking chip and board geometries, higher speeds, and greater densities, legacy test technologies no longer provide the access and defect coverage they once did,” said Adam Ley, chief technologist, Non-intrusive Board Test and JTAG, and one of the three authors of the tutorial. “Even the slightest operational variance outside of the board’s specified tolerances could cause problems later when performance degrades or intermittent system crashes occur.”

Slight variances and defects on circuit boards are more difficult than ever to detect and diagnose, Asset says, and can result in system crashes and degrade performance later on because their harmful effects are cumulative.

The program, “A Tutorial: Detection and Diagnosis of Printed Circuit Board Defects and Variances” is available at http://asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/Tutorial-Board-Test-DDR3-DDR4-Memory-Serial-IO.

 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 


Printed Circuit Design & Fab Magazine on Facebook