Successful fanout solutions provide escape routing for a combination of serial and parallel nets.

This is the fourth in a series of articles on BGA routing methods. My objective is to reveal the routing problems often associated with large pin-count BGAs, and provide the PCB designer with effective techniques that enable higher route density and reduction of layer count.

The effectiveness of a fanout pattern on large BGAs contributes significantly to the route-ability of a design, which impacts the layer count and affects the cost of the board fabrication. The fanout of a BGA is only a part of the routing solution, which may also include escape traces and general interconnect routing of the pins. The goal of the BGA fanout effort should be to eliminate the BGA routing as the primary contributor to increasing layer count while maintaining signal integrity and fabrication yield requirements.

In a theoretical approach to BGA breakout, the BGA is analyzed outside the context of a real design. This kind of solution is a mathematical excercise in layer reduction that makes unrealistic assumptions and disregards SI requirements.

Unfortunately, reality requires much more than just a mathematical solution. Deriving fanout patterns in a theoretical realm can actually be fairly simple, but finding effective fanout patterns when all the design and packaging challenges must be considered is a much more difficult problem.

It would be ideal to have power and ground pins only in the center of a BGA, however, power integrity requires they also be distributed among the signal pins. This distribution is rarely in neat columns and rows, which would open up considerable routing space.

Figure 1 shows an ideal distribution of ground pins (green). If the BGA had ground pins aligned this way, and if the mount layer was a GND plane, then you would see additional room made available on the inner routing layers.

Unfortunately, most FPGA vendors distribute the power and ground pins around the BGA or use some pattern other than columns and rows. The purpose of distributing power and ground pins is to improve the power integrity. Xilinx often uses a “Sparse Chevron” pattern as shown in Figure 2. In this figure the ground pins are green and the power pins are brown.

There may be some ASICs that have power and ground pins aligned in columns and rows, however, such an ideal condition is not common, and therefore effective fanout and routing solutions must incorporate other ways to reduce the layer count.

Most large BGAs have a combination of serial and parallel nets that must be routed as differential pairs and single-ended nets (respectively). Some FPGAs also allow for nets to be programmed as either serial or parallel. These devices support multiple I/O performance standards that could require differential routing.

Differential pairs and single-ended nets require different trace widths and spacing to maintain desired impedance, and although it is possible to use the same spacing rules inside the BGA area, impedance discontinuity may become significant in some high-speed circuits.

For example, it is common to have a target of 50 Ω for single-ended nets and 100 Ω for differential pairs. Of course the stack up thicknesses and materials will affect the impedance; yet it is common to see a 0.15 mm (6th) for differential pair spacing while single-ended nets can have 0.1 mm (4th). Actual trace widths and clearances will vary depending on the specific high-speed and fabrication requirements for each design.

If the fanouts are positioned such that differential pairs need to be split to maintain the trace width and clearance rules, that could also cause significant signal integrity problems, as illustrated in Figure 3.

Summarizing, a theoretical fanout and breakout solution that does not take into consideration the potential for varied trace widths and clearances is not very useful. The problem becomes even more difficult when each I/O pin or bank of pins can be programmed to require either differential pair or single-ended routing.

An effective fanout solution that enables the most efficient escape routing should be flexible enough to support the trace width and clearance requirements for a mixture of serial and parallel nets.

Through-Vias

There are not many fanout options, due to the large via pad relative to the 1-mm ball pitch. Either a “Quadrant Dog-Bone” or “Via-in-Pad” method is appropriate.

Theory: Removing Vias

One method proposed to increase route channels on inner layers is not to use fanout vias where possible, for power, ground and unused pins. When using through-vias, there is very little benefit in not adding fanout vias for the 30% to 50% of the BGA pins that will likely be assigned to power, ground or unused. The power and ground pins will be assigned to the center of the device and distributed among the other pins. It is highly unlikely that they, or any unused pins will be distributed in columns and rows.

When using through-vias for fanouts, rather than trying to gain a few route channels by eliminating connections to the planes, it is best to gain the power integrity benefits by adding fanouts for all power and ground pins. In Figure 4, it is clear that the vias for power and ground are scattered such that even if they were removed, little would be gained. The outer perimeter of through-vias dictates the space available for routing, and at least in the case of the Virtex-4, few of them are assigned to power and ground.

If an ASIC can be packaged to provide adequate power integrity and have the power and ground pins aligned in such a manner so as to increase route channels (by not using fanout vias) that would be a good design, but this is likely to be a rare occurrence.

Quadrant Dog-Bone

This fanout pattern has the fanout vias in the center spaced between the ball pads, and angled in one of four directions.

Advantages over via-in-pad.

• It opens up additional routing channels in the center row and column, giving room for two or three more routes per layer, which could contribute layer reduction, seen in Figure 5.
  
• On the side of the board opposite the BGA mount, the column and row channel gives a convenient place to add capacitors and pull-up resistors.
  
• A lower cost and less risk of soldering problems related to the via-in-pad.
  

Disadvantages over via-in-pad.

• When using a ground or power plane on the BGA mount side, the fanout via pads prevent a continuous plane fill under the BGA.
  

Shifting Through-Vias

Choosing to place the fanout via outside the center of the ball pad array has a relatively little benefit to routing due to the lack of space. Any benefits depend on the design rules. You could move the vias off-center somewhat in order to form columns and rows, but for every additional route channel opened on one side, it will close a route channel on the other – the net result being the same number of route channels across the entire BGA.

However, if the design rules are such that differential pairs cannot be routed together between the through-vias, and a little more space is required, then shifting through-vias slightly might make sense.

In Figure 6 and Figure 7, note that by shifting the vias to the left on one column and to the right on the next column, you gain 0.17 mm in one and lose 0.17 mm in the other. These values could vary, depending on your ball pad size and clearance rules. This option might be useful if you have some critical signals that require greater spacing within the BGA breakout area.

Another reason for shifting through-vias while using Quad Dog-Bone patterns is to maximize the amount of plane fill on the mount layer. Again, any benefit is dependent on the design rules.

Via-in-Pad

This pattern has a simple solution, which is to add a through-via in the center of each of the desired BGA ball pads as seen in Figure 8.

Advantages over quadrant dog-bone.

• If you have a ground or power plane on the BGA mount side, the fanout via pads allow a continuous plane fill under the BGA.
  
• If you do not use the mount layer for a plane, then you have an additional routing layer for the BGA – albeit a surface layer, which may cause impedance problems when using high-speed nets.
  

Disadvantages over quadrant dog-bone.

• There are no additional route channels in the center column and row.
• There is less room for capacitors and resistors on the opposite side under the BGA, since the fanout via array is full.

If the BGA has unused pins and you do not add fanout vias for them, there will be available room for components.

• There will be a slightly higher cost for filling the vias and ensuring a smooth surface when soldering the ball pads.
• There is some risk of BGA soldering problems (delamination or pop corning) with via-in-pad when using lead-free solder. An experienced assembly company should be able to manage this risk.
  

Better Methods

Although through-via stackups generally provide the lowest cost fabrication, the large size of the via severely limits your ability to maximize route density and therefore leads to excessive layer count. The next article will clearly demonstrate the benefits of using blind and buried vias. PCD&F

Charles Pfeil is an engineering director for Mentor Graphics, Systems Design Division; charles_pfeil@mentor.com; mentor.com/pcb.