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Mentor Technology Leadership Awards Call for Entries
Written by Kathy Nargi-Toth
Thursday, 10 January 2008
WILSONVILLE, OR - Mentor Graphics Corporation announced a call-for-entries for its 20th annual Technology Leadership Awards
competition. The competition recognizes engineers and computer aided
design (CAD) designers who use Mentor tools to address complex PCB
systems design challenges and produce industry-leading products.
Entries can be submitted from January 10th through March 14, 2008. Entrants can apply online at www.mentor.com/go/tla.
Judging will be based on overcoming complexity challenges, such as
small form factor, high-speed content, design team collaboration,
advanced PCB fabrication technologies and design-cycle time reduction.
Judging will start in mid-March and winners will be announced at the
PCB Design Conference East, Tinley Park, IL in May 11-16, 2008.
PCB
industry experts will judge the contest. This year’s judges include
Happy Holden, senior technology specialist of Mentor Graphics; Gary
Ferrari, technical support director, FTG Circuits; Pete Waddell, vice
president of UP Media, publisher of Printed Circuit Designs & Fab
Magazine; and Rick Hartley, senior principal engineer, avionics
division of L-3 Communications.
Entrants can submit their design accomplishments in any of six categories representing a wide variety of industries:
· PC computers and peripherals
· Consumer electronics and handhelds
· Industrial control, instrumentation, security and medical
· Military and aerospace
· Telecom switches, network servers, base stations and computer mainframes
· Transportation and automotive
“Mentor Graphics is committed to the PCB systems design community, and our PCB Technology Leadership Awards
contest provides the opportunity to showcase the most innovative and
talented designers worldwide,” said Henry Potts, vice president and
general manager, systems design division, Mentor Graphics. “The program
continues to attract the most skilled users of our PCB systems design
tools and Mentor expects this year’s competition to be bigger than ever
with entries from virtually all the major electronics countries in the
world.”
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CSP/BallNest Socket Provides Consistant Test and Burn-In
Aries Electronics introduces the CSP/BallNest Hybrid Socket for test or burn-in of chip scale package, ball grid array, microBGA, land grid array and prototyping. It can be used on any device having a pitch of 0.30 mm or larger. Features include a lid that nests each ball termination into the socket for a reliable connection and a four-point crown providing scrub on solder oxides. It has a signal path of 0.0777 inches and provides minimal signal loss for higher bandwidth capability. Estimated contact life is 500,000 cycles, and the socket is available in custom materials, sizes, configurations and platings. www.arieselec.com