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Zuken and Aldec Partner for Complete FPGA Design, Verification Flow
Written by Tracy Heffner
Thursday, 31 May 2007
MUNICH, Germany and WESTFORD, MA – Zuken and Aldec Inc. have formed a partnership in order to combine Zuken’s knowledge in system- and board-level electronics design and verification with Aldec’s mixed HDL verification technology. The two companies will reportedly offer a combined design and verification flow for flexible field programmable gate array (FPGA) devices on PCBs. At this time, the partnership will focus integration efforts on Zuken’s enterprise-wide PCB design suite, CR-5000.
“There is a growing challenge associated with adopting FPGA devices. By forging this partnership with Aldec to introduce a complete design and verification flow, we are tooling engineers with the latest technology to apply FPGAs with the minimum of effort,” said Gerhard Lipski, Zuken Americas CEO and European general manager.
“This integrated approach saves significant time, reduces errors and allows individuals to work on different aspects of the PCB and/or FPGA design simultaneously, at the same time, reducing re-work that may be involved in manual sharing of design data, and minimizing the typically error-prone methodology involved in manual data transfer and modification,” added Lipski.
Initial development will allow designers to launch Aldec’s mixed language simulation technology from within CR-5000 System Designer for access to project-specific design data. It will be possible to perform FPGA timing simulation for the complete design rather than for the individual FPGAs in isolation. Additionally, within CR-5000 Board Designer, layout engineers will be able to perform pin swaps that will concurrently update all PCB and FPGA design data, rather than only be able to perform this on request from the FPGA implementation engineer.
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