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Oki Analog Block Development Speeds Up with Cadence |
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Written by Tracy Heffner
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Wednesday, 08 June 2005 |
TOKYO and SAN JOSE – Cadence Design Systems Inc. and Oki Electric Co. reported that Oki has achieved five times faster design turn-around-time for its analog blocks than with its previous design methodology and has successfully completed 30 reusable analog intellectual property (IP) designs using Cadence Virtuoso NeoCircuit technology.
"Cadence's Virtuoso NeoCircuit technology has become a key component of Oki's analog IP creation," said Ichiro Yamamoto, senior manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company. "We are proud to announce that we have established a new design culture based on Virtuoso NeoCircuit with our proprietary IP templates. This Cadence technology allows us to compete more effectively with other leading manufacturers in this market segment."
Oki's designers wanted to reuse the analog IP they had already created without having to manually repeat design work. The use of this fully tested IP reduced the need for expensive verification cycles and silicon re-spins. This had the added benefit of allowing designers to focus on their core competencies.
"Cadence is very pleased that Oki has successfully established its analog design environment in less than a year and, in the process, created over 30 analog IP designs based on the Cadence Virtuoso NeoCircuit technology," said Felicia James, vice president and general manager, Cadence Virtuoso custom design platform. "This success is proof of Oki's advanced analog design innovation."
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