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Virage Logic, Cadence Further Low-Power Design
Written by Tracy Heffner
Wednesday, 08 June 2005
San Jose – Cadence Design Systems Inc. and Virage Logic Corp. reported in a press release that the Cadence Encounter low-power digital IC design flow now supports power saving features of Virage Logic's IPrima Mobile Semiconductor IP Platform's Ultra-Low-Power (ULP) standard cell library. This allegedly enables a low-power methodology that features full support of offset biasing, a substrate bias technique that can reduce device leakage up to 3.5 times. Cadence is said to be the first EDA vendor to validate support of this technique for standard cell logic. Customers are now able to utilize the full capabilities of Encounter IC implementation for producing leading-edge system-on-chip (SoC) designs with all of Virage Logic's Area, Speed and Power (ASAP) Logic and IPrima Mobile cell libraries in a fully validated design flow. The Encounter low-power digital IC flow performs the routing of the additional bias rail and selects the proper tap option that enables the offset biasing option of the IPrima Mobile ULP cell library. "Encounter is the first routing technology to demonstrate the Virage Logic IPrima Mobile Platform ULP cell library low-power offset biasing options," said Brani Buric, senior director of business development and platform product marketing at Virage. "Although offset biasing is not new to the industry in terms of providing leakage power savings, this proven methodology is unique in addressing biasing capabilities at the SoC design level."
"This is an important follow-on to our news last February about our low-power design collaboration with Virage Logic," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "As Encounter continues to advance its technological capabilities, we can work with our mutual customers to address the continuing evolution of advanced techniques required in low-power design."
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