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New IP Core For FPGA Aims For Greater Computing Densities
Written by Tracy Heffner
Tuesday, 24 May 2005
RENO, NV, May 24, 2005 - 4DSP Inc. has released its Floating Point Fast Fourier Transform core that is IEEE-754 compliant. This IP core was designed for use in the newer generation of high performance programmable devices, available from FPGA vendors like Xilinx and Altera.
According to a press release, the FFT core performs and transforms on complex data ranging from 256 points to 1M points with external memory, if necessary, such as QDR SRAM, closely coupled to the internal logic of the FPGA. Based on a radix-32 architecture, it reportedly allows users to change the transform length without having to reconfigure the programmable device.
"We did not expect to reach this level of performance in an FPGA. This has typically been done in an ASIC, which is increasingly more expensive to develop and requires specific board architecture. To produce a flexible and lower cost device, that is capable of performing a 1024 points Floating Point FFT in 11.4 microseconds using a single core, is far beyond our original expectations," says Pierrick Vulliez, 4DSP's CTO. "For example, when applied to Video 2D transforms with 1024 x 1024 images, a single core can process 42 frames per second."
New advancements in FPGA gate densities, combined with tightly written VHDL cores, allegedly allow multiple cores to co-exist inside a single FPGA device. In new chips like the Altera Stratix-II and Xilinx Virtex-4 FPGAs, it is said that four cores can be implemented in parallel, offering a double-digit acceleration factor compared to currently available floating-point DSP devices.
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