Signal Integrity and PCB Physical Parameters Print E-mail
Written by Carl F. Hornig   
Tuesday, 31 January 2012 22:49

Effects of passive geometry or topography attributes common to PCB layout.

High-speed signal integrity is often influenced to a greater extent by the printed circuit board’s physical parameters than the chosen laminate material. High-speed laminate materials with a low dielectric constant or permittivity, , and dissipation factor, , determine signal propagation velocity, dispersion and attenuation. While these two parameters,  and , certainly influence high-frequency attenuation and circuit rise time, their effects may be compensated for through pre- or de-emphasis and equalization. Through the application of glass styles, high-speed laminate properties are becoming more isotropic. Upon selecting a laminate material, the and remain static. Thus, the remaining variables are those associated with the PCB layout. The purpose of this discussion is to identify various passive geometry or topography attributes common to the PCB layout, their effects and potential corrective actions.

Impedance discontinuities, channel-to-channel crosstalk, skew, and unwanted reflections associated with the PCB geometry or topography adversely influence gigabit transmission clarity. Those traces exceeding the critical length associated with signal rise time behave as transmission lines. The need to apply transmission line concepts may be ascertained by defining the signal path critical length. The propagation velocity, conversely the propagation delay, , and critical length may be calculated as follows, where is the speed of light and is the dielectric constant at the operating frequency:







The critical length may be estimated by calculating the distance a pulse travels in one-half the rise time of the logic device or family selected:



Outer layer traces, which are subject to the PCB plating process and have a metalized surface finish delineating the traces during the etch process, may have undesirable magnetic properties and a greater delineation tolerance than that seen with an innerlayer trace. Due to improved trace delineation, reduced electromagnetic interference, and not being influenced by a metalized surface finish, transmission line innerlayer traces are often preferred.

Passive interconnect losses and signal distortions may be classified per Table 1. The dissipation factor or loss-tangent and skin depth effects associated with a conductor’s cross-section and surface roughness drive frequency-dependent losses. The most prominent would be loss attributed to dipole oscillation within the laminate material.





Conductor loss varies proportional to the square root of the frequency:



As a fast rising edge propagates, fewer high-frequency components remain, and the rise time increases. This is the chief cause of inter-symbol interference, ISI. Corrective actions include:

  • Increase conductor width.
  • Lower dissipation factor.
  • Pre-emphasis (High-frequency addition).
  • De-emphasis (Low-frequency reduction).
  • Equalization (Add frequency-dependent gain at receiver).

Impedance discontinuities associated with trace routing reflect a portion of the signal being transmitted and contribute unwanted transmission line noise and ISI. Reference plane geometry and continuity, trace width variations, and the plated through-hole (PTH) and via structures may contribute to reflections. Corrective actions include:

  • Microstrip and embedded-microstrip having an uninterrupted and electrical stable reference plane, minimum pad diameters and vias, and avoidance of abrupt modifications to the trace geometry, such as 90° turns.
  • Stripline and offset stripline trace routing should employ similar parameters as recommended for microstrip and embedded-microstrip.
  • Ground planes should have low impedance returns, reducing the opportunity for ground bounce and common mode interference.
  • Avoid ground planes with rectangular slots, square openings and placing embedded traces within the plane.

Routing trace connections through an impedance-compensated via or PTH providing a connection between multilayer signal traces minimizing capacitance and controlling via or PTH stub length reduces reflections emanating from layer-to-layer connections. While the ideal PTH or via connection may not often be achievable, the following may be employed to assist signal clarity:

  • Minimize PTH capacitance by removing non-functional pads.
  • Minimize via and PTH diameter and associated pad.
  • Maximize anti-pad clearance.
  • Minimize PTH stub and avoid having a stub whose length is a quarter wave length.
    • Wave length.
    • Length.
  • Stubs shorter than 0.050" appear capacitive and slow down the edge rate.
  • Stubs longer than 0.050" act as resonators.


Channel-to-channel crosstalk is both capacitive through electrical field coupling and inductive through magnetic field coupling. Capacitance-coupled crosstalk has the same polarity as the active signal. Inductive-coupled crosstalk at the driver or near end has the same polarity as the active signal and the opposite polarity at the receiver end. Near end crosstalk (NEXT) or backward crosstalk is the sum of both capacitance and inductive coupling, and thus of greater magnitude than far end crosstalk (FEXT). Coupled trace lengths beyond which crosstalk contributes to signal interference:

NEXT

FEXT 

Minimizing crosstalk can be achieved by:

  • Microstrip with spacing between adjacent single-ended traces and/or adjacent differential pairs greater than twice the distance to the reference plane.
  • Offset stripline with spacing between adjacent single-ended and/or differential pair traces greater than twice the distance to the closest reference plane.
  • Symmetric stripline with spacing between parallel single-ended and differential pair traces greater than the distance to the reference plane.

In addition to closely spaced parallel traces, via fields may also contribute to crosstalk. Minimizing stub length reduces reflections and unwanted via field crosstalk. Alternating via pairs in a via field, such that every other via pair’s coupling is at 90° to the previous contributes to reducing crosstalk.

Intrapair skew resulting from time delays associated with differential pairs is driven by:

  • Difference in conductor lengths between differential pair traces and can be avoided through proper routing, assuring individual trace length equalization.
  • Another source, the difference in between the glass weave and laminate resin affects the average signal propagation velocity between traces within a differential pair and contributes to oscillating impedance shifts. The glass and resin varies from approximately 6.0 to 7.0, and 2.5 to 4.0, respectively. Traces predominantly referencing glass having a greater  will have a lower impedance and greater propagation delay than those traces predominantly over resin.

Minimize intrapair skew:

  • Selecting a class style providing a homogenous weave and reducing the potential to have each trace within a differential pair inadvertently routed continuously over substrate regions having different values.
  • Placing the backplane or system card on a process panel to maximize opportunity for traces within a differential pair to have an equivalent distribution, considering the laminate’s epoxy and glass weave structure.

The system noise budget with respect to gigabit speeds and subsequent bandwidth and bit error rate will determine the need to apply the material and physical principles discussed. If the laminate material has a characteristic loss tangent or dissipation factor and skin depth losses within the copper trace, signal strength decreases with increasing frequency. And noise increase with increasing gigabit speeds through crosstalk, impedance mismatches, unwanted reflections radiating from via or PTH stubs, and skew. The object of a circuit board design is to preserve signal strength and clarity and reduce opportunities for distortion and noise resulting from the printed circuit board material and physical parameters.

Bibliography

1. H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993.
2. T. Edwards, Foundations for Microstrip Circuit Design, John Wiley and Sons, 1983.
3. C. Coombs, ed., Printed Circuit Handbook, McGraw-Hill, 1995.
4. R. Pangier and M. Gay, “Making Sense of Laminate Dielectric Properties,” Printed Circuit Design & Fab, January 2009.
5. G. Ravindra, “PCB Dielectric Materials for High Speed Applications,” Printed Circuit Design & Fab, December 2008.
6. D. Brooks, “The Skinny on Skin Effects,” Printed Circuit Design & Fab, December 2009.
7. J. Coonrod, “Understanding PCBs for High Frequency Applications,” Printed Circuit Design & Fab, October 2011.
8. J. Howard, “Quadrature-VIA layout,” EDN, December 2011.

Carl F. Hornig is a retired engineer who most recently worked at Sanmina-SCI’s backplane division; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Wednesday, 01 February 2012 18:08
 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 


Printed Circuit Design & Fab Magazine on Facebook