Making Smart Vias Print E-mail
Written by Patrick Carrier   
Monday, 31 October 2011 20:38

Or how a stitch in time could save the design.

Printed circuit board design is actually quite ingenious – layers and layers of thin traces connected to each other by via holes drilled in the board and plated. From a signal integrity standpoint, however, a via is a ridiculous structure. We take such great care to make sure traces are a very precise width, spaced a very precise distance from a reference plane or pair of reference planes to get just the right impedance on the traces, and then connect them to (relatively) giant holes drilled into the board. It is actually kind of funny. But at the same time, it is a necessity of designing any modern PCB, and one that can be overcome by making smart vias.
A “smart via” is a via that has very little effect on the signals passing through it. That typically means having characteristic impedance equal to that of the traces connected to it. But the term “characteristic impedance” can be misleading when it comes to vias, as it implies a uniform cross-section. Vias are actually very nonuniform, and in some cases, depending on the application, require use of  a 3D field-solver to be properly characterized and simulated. This is usually true of faster differential interfaces in the 10Gbps realm. For single-ended interfaces, however, it is often essential to include the power distribution network (PDN) of the board in the via model. The reason for this is that the entire current path is essential for modeling the via performance. For AC signals, this means an incident path (the via) and the return path (the PDN).

For slow single-ended signals, a simple L-C circuit will sufficiently model the “impedance bump” produced by the via. But as the rise time of the signal approaches the electrical length of the via, it becomes important to include greater detail in the model, such as more accurately including the effect of the via return path. The return path for a single-ended via is the board PDN, which will consist of stitching vias, decoupling capacitors, and power and ground planes. An insufficiently “bypassed” via will have a poor return path, which will appear as added inductance (or added impedance) that will degrade the signal. This can be seen in Figure 1, where a signal via is analyzed.



This lone via was placed on a 6" x 6" PCB with a six-layer stackup, and analyzed for cases where there was no stitching via (shown in light blue), one stitching via placed 0.060" away (shown in green), two stitching vias (pink), and four stitching vias (yellow). Ideally, we would completely surround every signal via with stitching vias to make it look more like a coaxial cable, but as the results show, four stitching vias are sufficient to minimize the added effect of the return path impedance. Clearly, even a single stitching via makes a dramatic improvement.

Similarly to traces, a via return path is important not only to maintain the correct impedance, but also to control crosstalk. If there are insufficient stitching vias (or bypass capacitors) to provide a return path, or if multiple signal vias share the same return path, a great deal of via-to-via crosstalk can occur.

With differential vias, the pair of vias has a relatively self-contained return path, especially if the channel is well balanced. So for differential vias, which are typically used for faster serial signals, the most important aspects of via design lie in the via size, spacing and layer span. The size and spacing of the vias determine their characteristic impedance, and vias typically represent a low impedance compared to PCB traces. Typically, the approach is to increase the via impedance as much as possible by using smaller drill sizes, smaller pads, and larger antipads. Also, vias could be moved farther apart, but this reduces coupling that may require a number of stitching vias to counteract. The other big problem at gigabit speeds is the stub effect of the via. Large stubs at gigabit speeds can degrade signals to the point of failure. This can be reduced by controlling the layer span of the via, or by eliminating or reducing stubs by using blind vias or mechanically backdrilling through-hole vias.

As shown in Figure 2, eliminating the via stubs improves a clearly failing signal (shown in green) to one that is marginally passing (shown in yellow). At these speeds, it is important to model the unique sections of the complex differential via pair. This allows capturing the interaction between the vias and each other, the board planes, any nearby stitching vias, as well as the traces connected to the vias.



The type and speed of the application will determine which concerns are greatest when designing vias. With this in mind, and with the right tools, it is certainly possible to design smart vias.

Patrick Carrier is a technical marketing engineer for high-speed PCB analysis tools at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Tuesday, 01 November 2011 16:51
 

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