Mentor Upgrades HyperLynx High-Speed Design Tool Print E-mail
Written by Mike Buetow   
Wednesday, 30 January 2013 14:34

HyperLynx now includes advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance.

Simulation speed has been increased up to five times faster than previous versions. Analyzes potential high-speed design issues that can impact signal integrity, power integrity, and electromagnetic interference (EMI) performance. Decreases the amount of channel modeling that requires 3D analysis with advanced area fill-aware 2.5D planar trace extraction. Models variations in signal trace impedance or delays due to non-ideal planes and references (complex area fills with voids and cuts). Resulting impedance variation effects are included during time domain simulation and s-parameter model extraction. Provides full 3D extraction and modeling. Is said to avoid accuracy problems for circuits involving short transmission lines, common when modeling PCB-trace meanders. Wizard supports DDR3L and DDR3U supply levels by incorporating required derating tables, timing models, and voltage levels, plus test-load compensation of signal launch delays. Ship in March and will be interfaced with all major PCB layout tools including the Expedition Enterprise, Board Station and PADS, Cadence Allegro and Zuken CR.

Mentor Graphics, www.mentor.com/hyperlynx

 

 

 

 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 


Printed Circuit Design & Fab Magazine on Facebook