LabVIEW FPGA IP Builder add-on uses Xilinx Vivado High-Level Synthesis technology to simplify high-performance field-programmable gate array (FPGA) algorithm design. Enhances productivity by reducing need for manual optimization of high-performance algorithms. When functional behavior and design constraints are specified, automatically generates a hardware implementation to meet requirements. Integrates with LabVIEW and the LabVIEW DSP Design Module. Features include increased FPGA design abstraction for enhanced productivity, improved algorithm performance and resource utilization, separation of code and design constraints facilitates IP reuse, seamless deployment to NI FPGA-based devices.

National Instruments, www.ni.com