SystemSI signal integrity analysis software is for end-to-end simulations of high-speed signal interfaces. Has block-based editor, support for standard modeling formats, automated model connections and accurate simulation. Can be used at the pre-layout stage, post-layout stage, or anywhere in between. TLine Editor and Via Wizard are available. Model connections are automated with open Model Connection Protocol format. Is available in SystemSI – Serial Link Analysis and SystemSI – Parallel Bus Analysis. The latter builds on capabilities introduced in Channel Designer software to analyze high-speed SerDes designs. Parallel Bus Analysis brings the same level of automation and accuracy to the design of high-speed bus interfaces such as DDRx memory interfaces; enables quick analysis of timing margins for DDRx memory interfaces; considers multiple effects concurrently, including dielectric/conductor loss, reflections, crosstalk, inter-symbol interference and simultaneous switching noise.

Sigrity, www.sigrity.com