| IPC-2581 Consortium Validates Bare Board Fab Data |
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| Written by Edward B. Acheson | |||
| Thursday, 17 May 2012 19:33 | |||
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First stage of a three-phase test plan is successfully completed. Whenever a new technology is discovered, someone has to be first to try it. The PCB design and manufacturing business in particular expends a great deal of time and money to refine a process based on a new technology. Someone has to work out the kinks, discover misplaced assumptions, experience delays in first manufacturing runs; the list goes on. But when someone is the first to succeed, everyone learns by example – that is, if the initiator is willing to share their experience. The first activity of the technical work group was to create a validation plan based on the three major areas of PCB production: bare board fabrication data, assembly data, and test data. Once the plans were put in place, an aggressive schedule was set for each of these three phases. The first phase of the test plan was to validate bare-board fabrication data contained within the IPC-2581 single-file format. Phase I testing compared the IPC-2581 fabrication data against today’s existing export data formats (artwork, NC drill and NC route) for accuracy and completeness. Cadence and Zuken provided initial test cases from internal designs, followed by real design data from IPC-2581 Consortium members NVIDIA and Fujitsu. Tools provided by ADIVA, DownStream Technologies, EasyLogix, and Wise Software consumed the IPC-2581 data and ran comparisons against the artwork, drill, and route data.
Figure 1. Path of data, from original CAD system to output format to viewer.
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| Last Updated on Thursday, 17 May 2012 19:44 |
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